UCIe

So it may be connecting CPU with an AI accelerator, AI accelerators to memory.

So you may have heard all the standards that are on your channel, PCIe, HPM, LPDDR, UCIe, die-to-die, and Ethernet.

And these are really the five key interface IPs, and that's what customization is all about.

Okay.

So if you look at the whole spectrum, there's the IP.

there's which foundry and process node it's available on, and then there's the, I'm gonna say, kind of envelope for the standards compliance.

And a good way to think about that is, A PCIe standard, I know we keep talking about PCIe, or a UCIe standard.

Actually, we should start with UCIe.

The next generation Raya 2 is the more important next step.

It's described as a dual-chiplet processor with more than 96 NeoVerse V3 cores connected to UCI-E, with tape-out expected in 2027 and deployment beginning around 2028.

It is already planned for the CPU partition of Europe's second exascale system after Jupiter called Alice Recoque.

Europe also has Intel's advanced manufacturing operation in Ireland, all of which means that The EU is moving ahead, even if at a relatively slow pace, with its exascale and technology sovereignty strategies.