UALink

So reliability is really important for scale-up.

And especially for UALink and VLink type of interconnect.

So they try to put the interconnect inside the box, inside the system box.

And then they want to put the interconnect right next to their XPUs, GPUs, and NPUs.

One is called ESUN, which stands for Ethernet Scale-Up Network.

And then the second standard is a standard called UA-Link, which is ultra-accelerator link, right? Those are the two standards.

A lot of the people are adopting eSUN in the near term.

But as Barun pointed out, the difference is that the latencies need to be a lot lower.

So, for example, the scale-up switch, okay, is being built by us.

So we are building the scale-up switch based on open standards.

Like Rajiv mentioned, there are two open standards, ESUN and UA-Link.

And there are brand new standards that got standardized like late last year kind of a thing.

And then there's a protocol layer that sits on top of that.

And so when you look at NVLink and UALink, those can ride on top of OCI or they could ride on top of

Ethernet.

right? So they can use either one.

And the unified setup is not just connecting the front sides of these servers together.

They're also connecting the GPU clusters on the back end through things like UALink and NVLink and things like that.

So they have to have a massive amount of throughput.

Yeah, and that's incredibly true.

It was baked into RAIO-1 before several industry projects, C6, Gen Z, OpenCAPI, CXL itself, effectively converged around CXL, with the idea that future CXL specification would blend them all into a single proposed standard.

With the emergence of AI workloads and the proposed GPU-focused ultra-accelerator link, UA link, CXL has morphed into a CPU-focused connectivity standard for CPU-to-CPU, CPU-to-memory, and CPU-to-GPU connectivity.

For RAIO-1, CCX does the job and lays the foundation for RAIO-2.

Now, RAIO-2 is probably already largely baked as well, but I would expect that things like the Neoverse V3 compute architecture, newer vector capabilities, memory hierarchy, and chiplet design to have been frozen before the exact CXL generation.