Three-dimensional integrated circuit

I think another answer is actually really interesting technically.

In the area of 3D IC, when you're stacking one die on top of the next die, that actually has a profound impact on IP.

Because now what you need to do is you need to make sure that in your IP, you have the ability to route both signal and ground from one top die to the bottom die.

and you need to do that in a way where you're not disturbing the circuitry of the ip so for example in a high speed physical design you want to make sure you're not you know having noise coupling into your ip so we work really closely with um our lead customers on 3d enabled um ip to make sure that they can route power and signals through our IP rather than around the IP, which has been the traditional paradigm.

You know, I think the single biggest challenge you hear universally from our customers is the thermal management, because you're stacking an enormous number of chips in a small area, dissipating huge amount of power.

So how do you successfully distribute that power, that thermal distribution, without creating hot spots into the dye that can yield performance problems or can yield much more significant problems? It can result in things like cracking of the package, delamination of the package, if you're not modeling the thermal characteristics well.

So this is by far the single biggest challenge moving into 3D IC is how do you manage the thermal characteristics very well.

And going back to an earlier comment, one of the benefits of the ANSYS acquisition is they have the leading platform for thermal modeling inside a package and inside a chip.