Serial Peripheral Interface

to be, I mean, they need to be implemented in QEMU itself.

So, um, uh, if you want to, um, yeah, I'm trying to think of like SPI, for example, I don't think we have, um, uh, SPI support in any of the, um, the, the QEMU, um, target for express, if you would, I think it also simulates, um, things like the, uh, the RTC and the low power modes on, on the, on the CPU.

So you can actually run a fair bit of code of the code samples that, um, Zephyr supports and the Espressif-specific samples as well on those QEMU boards.

So yeah, it's nice to see.

It's going to eat quite a bit of resources.

The problem for me is that pretty much all of the input driver, which are the ones I maintain, generate an interrupt, and then the interrupt is handled on the work queue.

And the work queue is going to be either I2C or SPI for 90% of them.

And it could be a problem if your work queue is busy or if your application needs the work queue to execute some other latency-sensitive stuff.

And so we can like, I'll give you some detailed specifics.

A lot of buses for controlling these things are on the I2C bus or I3C bus or on a SPI bus.

we can take with the FPGA and we can look at multiple channels, I2C, I3C, SPI, all at the same time.

And because the efficiency of being at a hardware level, we can look on a command by command basis on any of those channels.

So let's say we have a sensor that should only be reading information from its non-volatile memory store to tell it what to do.

There's a few lined up as well for VitaIO GPIO.

SPI, I2C, all those things are basically standardized by OASIS, if I'm not mistaken.

So it's actually pretty straightforward to add new drivers on top of the existing ring queue, whatever is the backend for VHIO.

One thing that this will enable, which I'm actually quite excited about, I mean, there's many use cases for VHIO, but one is in QEMU, right? And so that could literally enable people to run more in their QEMU environment, just like over the last decade.

So instead of having all of the fancy modulation, you just get the amplitude of the signal in the carrier and the 90 degree phase shift.

And then the idea is that you can represent any type of modulation by working on those two.

And I don't, normally you, on a discrete SPI radio, you can't access the data.

It may be used internally to implement the various demodulation, but it seems like this gives you access to the actual raw data,

And this is where my hardware security side gets excited.

I'll open the device and I'll start looking for things like JTAG, UART, SPI.

What is

this? What is all this?

But they got together and they said, like, "This is kind of, like, a lot of work to do it all together.

There's so many things like Wi-Fi and USB and networking, like internet stuff, that like, it would be great if we just had one source code that we could use instead of having to redo it ourselves." And so Zephyr is this real-time operating system, so it's managing what is running on the CPU within the microcontroller, but it's also doing a lot of other stuff like abstracting away I squared C and SPI and providing network stack and Bluetooth stack, all that sort of stuff, in a general way that, like, any vendor can now contribute to.

And so our interest in that is primarily for the fact that, like, a lot of vendors have brought in support or, or are, like, supporting their chips in Zephyr.

So by us building Circuit Python on top of Zephyr, we kind of get a lot of chips for free, where we don't have that much work to do to bring up I squared C or SPI or Flash or all these sorts of things.

We don't have to manage compilers, we don't have to manage compiler flags.

It's just, like, quite easy that once something is supported in Zephyr, we can get Circuit Python going in Zephyr, and it's been great.

It's a shield for a new EEPROM style.

It's one of those fancy, weird, hybrid SPI EEPROM things.

So it's an M95, a P32.

It's a shield just for a SOIC 8 chip, big shield, small chip.

It used to be like, oh, you have to deal with page arrays and limited rewrite cycles.

This is apparently a really, really good Flash if you want to abuse it, really.

So there's a shield to test it, but it's using the JEDEC SPI driver.

So just a heads up, this exists if you need it.

Serial monitor debugging mirrors industry standard practices.

Key expandability includes support for I2C and SPI sensors, PWM motor control, interrupt-driven timing, and RTOS concepts through FreeRTOS.

It runs entirely offline, has zero ongoing costs, and is USB-powered for prototyping.

The breadboard connection method frustrates younger learners, though.