Reduced instruction set computer

It felt like a recreation of the battles from the 1980s.

So in the 1980s when, uh, RISC, RISC proce- RISC processors were getting popular, people were using MIPS, instruct- millions of instructions per second as the metric, and, uh, but that was up to you to, how to define it, what you ran, all that stuff.

So the RISC companies were saying, "Well, you know, you can trust us, our numbers, but all those other, other bastards are lying." Right?

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there was an attempt to try and, uh, and the solution for the RISC one led to the peak companies getting together, collaborating on benchmarks, which were called SPEC, which were pretty...

That's what pretty much all your laptops and PCs ran on for decades, started by Intel.

And then along came the RISC products, R-I-S-C for reduced instruction set computers.

Arm was the leader in that.

And then Sci-5 is a good example of kind of the red hat of the RISC-V community.

But RISC-V was also a big project that came out of academia to have more of an open source RISC processor.

But the foundation for all of those is a fixed set of instructions that software commands.

And in FPGA, we don't have that.

So you're going in and configuring how those logic gates operate.

So do you know the name Jim Clark, by chance? Does that ring any bells? So Jim was a double E professor at Stanford, and he's an old friend of mine.

He started a company called MIPS, which was one of the first RISC architectures merged into Silicon Graphics.

He built Silicon Graphics to be one of the really important companies of the Valley.

Then he left and he started Netscape, which became the first browser company.

This is the ESP32-C61, which they described it as a similar design to the C5.

So it's a single core RISC-V.

I thought it was like a cheaper version of the C60.

ESP32 naming is getting weird.