LPDDR

And so that isn't that massive 3x improvement right there, but to really take advantage of, you know, the belief that models and everything are just going to get larger, we had to be able to scale to massive more channels.

And so we're, you know, partners with Credo Semiconductor that, and I've developed a memory chiplet solution that allows us to go from the maximum number of LPDDR, same type of memory that is in phones, laptops, et cetera, the max number of channels that you can find in any other products is on the order of, you know, 12, 12 to 16 channels.

And we go up to 72 channels of LPDDR5X with this decoupled memory chip solution.

Positron's next chip is called Asimov.

Prakash asked what disappears in networking and coordination when a whole model fits on one chip?

... have a, have a strategy and a path for them." You know, also, Positron guys, uh, Mitesh Agarwal, $5 billion valuation after 16 months.

I don't think I've ever seen anything like that before, and all, all they've done is taken a box of L- LPDDR RAM and an FPGA and find a way to run Chinese models without having to use an Nvidia chip.

And because-

Wow

And then they have another business, mobile and client, came in around 13.4 billion.

That includes like memory and storage use in smartphones, PCs, AI PCs, things like LPDDR memory, SSDs and other NAND based storage.

Because we all know, you know, SanDisk and NAND.

So they have that business as well, which is accelerating.

That's the problem Majestic Labs is trying to tackle with a different approach to AI system architecture.

The startup's developing its own AI compute chip, but rather than tightly coupling that compute with HPM, Majestic is building a server architecture that separates compute from memory and pools a huge amount of commodity LPDDR.

The company says its first generation system will support up to 128 terabytes of memory in a single server, with multiple compute accelerators accessing that memory as a shared memory space.

I spoke with Majestic Labs co-founder Shah Rabai about why he believes the conventional GPU plus HBM architecture is becoming economically inefficient, what the rise of agentic AI means for memory requirements, and how a radically different approach to memory could reshape the AI data center.

We don't create this very complicated multiple tiers of memory that like for the memory around the GPU you're running on, this is a performance you get.

If you need to access data on another GPU, well, now you're going through NVLink and NVSwitch, bandwidth is lower, but you can get to that data.

If you need to, access data that's sitting in the LPDDR that is hanging off of your host.

That's a whole other thing.

That's correct.

I saw that compared to the AI200, they both have the same amount of LPDDR in the card.

It's like 768 gigs.

768 gigs, yes.

And yet the 250, which is the first to have the HPC, has 18x the effective bandwidth, I believe is what the website said.

So again, just for everyone, can you remind us again why that HPC in the stacking is 18x the bandwidth as compared to in the 200, where presumably the LPDDR is a little

bit further away? So, first of all, the raw memory is a completely different concept compared to the actual memory bandwidth in itself.

So, this is LPDDR, which means we can actually pack.