Electronic design automation

The real, the real gold miners are the people attacking a vertical.

There are a whole bunch of startups attacking the, uh, EDA vertical.

Uh, uh, let me do, uh, one more.

Y- yeah, I, I'm sure...

So wh- when you do the verification plan, um, when AI do the verification plan, you would be happy with that? Um, are there gaps? How is it working?

It's, it's really up to, uh, the prompting s- prompting skills of the engineer if, if, uh, companies do not use some, some EDA tool, uh, uh, which is intended for this.

So engineer needs to have, uh, uh, experience with using AI on how to explain what to do.

If you, if you just say, "Create me a verification plan from this specification," it will create something.

Uh, so when it comes to, to generating coverage code, AI is, is very good at it.

But i-if we're talking about coverage closure, which is obviously probably, uh, more important or definitely more time-intensive work, AI can help, but this is also one of the gaps, uh, that, that traditional... not traditional, but, but mainstream platforms with the clean LLMs, uh, do not work that well.

So this is some-- this is also an area where AI EDA startup to-tools can show better results.

So what I'm talking about is that AI can help you close 90% of functional coverage, but this last time, 10%, which are also difficult for the human engineers will be very difficult for AI as well.

So if you involve multi-hop root cause analysis with a lot of data, LLMs will struggle.

So what I wanted to say is that this is where AI EDA startup tools can significantly help because they have mechanisms to better structure and interpret a lot of data and also there are mechanisms to help AI trace the steps back in a more efficient way than uh parsing a lot of raw data at the same time

okay so let's let's touch this uh bit down the the road but you know to emphasize on what works well um what ai does well and where it still falls uh behind compared to a chip designer Let's discuss a sample project.

You know, how do you start? What are the steps that you do in the project? And when you talk about each of the steps, and let's do that briefly because, you know, we can talk about that for a whole day.

you do the verification plan, would AI do the verification plan, you would be happy with that? Are there gaps? How is it working?

It's really up to the prompting skills of the engineer.

If companies do not use some EDA tool, which is intended for this, so engineer needs to have experience with using AI on how to explain what to do.

If you just say create a verification plan from this specification, it will create something.

You know, the way people talk about, like, uh, co-optimized, uh, co-optim- or, um, co-optimized design, right? Like, uh, for chip architecture, it's very opportunistic in terms of the types of things that you're working on, right? It's, it's kind of trying to tackle the design question from the wrong direction, right? Like you are saying, "Well, first I want to stack everything, and then I have to optimize," right? And what Huawei's saying is, actually if you take a step back and understand fundamentally what you're trying to do with the chip design, the first question you should be asking is not I should...

You know, how do I stack things together? The first question you should be asking is how do I reduce, you know, things like circuit path lengths, right? How do I reduce signal time so that I can increase, uh, the density of signals within a unit of time on the de- on the design? And then I can look at the whole template, right? Of, of different options I have on, on a, you know, and then kind of take, uh, you know, slap together the pieces I need in order to get to my requirements, right? And, and this, this fundamental difference in principle, right, design principle, right? Changes like, you know, what y- what kinds of engineering that you would want to do and, you know, how you would want to go about, you know, your chip design, right? And I think that that's the part that ends up getting missed, right? Is that you can, things can look similar in terms of, you know, specific practical, uh, details, but the, the design principles are different, right? And this, this is gonna reflect in, say, like how you do your EDA, uh, your E- your EDA designs, right? Like, um, what kind of EDA software you build and what kinds of design optimizations that EDA is, you know, is, is looking for, right? Like, these are the kinds of types of things that will change if you change the fundamental principle of design that you are, you know, that you are using, right? And I think, I think that's the part-

Yeah

... that ends up getting missed.

I mean, your EDAs will have to be able to handle like multiple layers of logic-

Right

...

in its design, right?

So if you involve multi-hop root cause analysis with a lot of data, LLMs will struggle.

So what I wanted to say is that this is where AI EDA startup tools can significantly help because they have mechanisms to better structure and interpret a lot of data and also there are mechanisms to help AI trace the steps back in a more efficient way than uh parsing a lot of raw data at the same time

okay so let's let's touch this uh bit down the the road but you know to emphasize on what works well um what ai does well and where it still falls uh behind compared to a chip designer Let's discuss a sample project.

You know, how do you start? What are the steps that you do in the project? And when you talk about each of the steps, and let's do that briefly because, you know, we can talk about that for a whole day.

you do the verification plan, would AI do the verification plan, you would be happy with that? Are there gaps? How is it working?

It's really up to the prompting skills of the engineer.

If companies do not use some EDA tool, which is intended for this, so engineer needs to have experience with using AI on how to explain what to do.

If you just say, create a verification plan from this specification, it will create something.

One line framing before we start.

AI adoption is now a real measurable revenue driver for EDA companies, not a slide in InvestTech.

That's the thread running through everything we are about to cover today.

Let's kick things off with the global DV con, the verification show from earlier this year.

The goal is to build an actual semiconductor workforce, not just publishing research kind of a talent.

That's genuinely wild to me.

And around the same time, there was a strong open source EDA moment.

A respected VLSI voice Shashi Obelisetti made the point that open source EDA has already proven it can design real working chips.