
Complex instruction set computer
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MENTIONS
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EPISODES
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PODCASTS
Search complete. 7 mentions across 6 episodes found for "Complex instruction set computer".
Oct 20, 2026
Nightlife Tech Talk with Peter Marks
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2:51Peter MarksGUEST
This dates back to the early 1980s.
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2:53Peter MarksGUEST
There was actually a British company called Acorn Computers, and they designed it as a simpler and cheaper alternative to the complex instruction sets chips, CISC, which were the ones popular at the time and still popular to some extent now.
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3:07Peter MarksGUEST
In 1990, Apple partnered with them and spun off Arm Holdings to develop a chip for their Newton PDA.
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3:13Peter MarksGUEST
Do you remember the Newton? It was this early PDA with handwriting on it, and that needed performance and low power.
Stanford CS153 Frontier Systems | Building the Frontier Ecosystem
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31:48Satya NadellaGUEST
Uh, it's a great time, by the way, f- to be in computer architecture.
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31:52Satya NadellaGUEST
Um, you know, I think, you know, when I started in, you know, in the industries when the Patterson book first came out, and that was the RISC versus CISC debate.
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32:01Satya NadellaGUEST
I feel like we are back at, uh, sort of a time like this where, uh, you can really rethink, uh, from the physical design of a data center, uh, to, uh, to...
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32:13Satya NadellaGUEST
By the way, the electrons, I mean, one of the p- places where I'm very excited about is the, the efficiency with which we can bring the electrons all the way, uh, to the CPU, uh, so that the tokens are, uh, that much more efficient, right, without all the losses in between.
Is Mobile Eating the PC? The MacBook Neo, the Googlebook, and the Laptop That Became a Phone
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13:14Artificial IntelligenceNARRATOR
Architecture feature Apple A18 Pro, MacBook Neo, Apple M4, Base, Intel Core Ultra X9 388H, Panther Lake, born in iPhone 16 Pro, iPad Pro, then MacBook Air Laptops Instruction Set ARMv9, RISC, ARMv9.
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13:33Artificial IntelligenceNARRATOR
2A RISC-X8664 CISC Manufacturing Node TSMC 3nm N3E TSMC 3nm 2nd General Intel 18A TSMC N3E CPU Core 6 2P plus 4E, 10, 4P plus 6E, 16, 4P plus 8E plus 4LPE, NPU AI performance 35 TOPS 38 TOPS approximately 50 TOPS max memory bandwidth 60GB per second 120GB, SUP to approximately 153GB, SA chip designed for a phone sits in the same table as two laptop processors, and it belongs there.
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14:17Artificial IntelligenceNARRATOR
Note the bottom rows, too.
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14:19Artificial IntelligenceNARRATOR
Every one of them carries a neural engine.
Why Q-Day Moved to 2029 | Arm Co-Founder Hermann Hauser
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2:59Hermann HauserGUEST
And interestingly, uh, the analogy with ARM, at least on the energy front, is very appropriate.
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3:05Hermann HauserGUEST
Uh, one of the things that happened [laughs], which was actually an American breakthrough, uh, the invention of RISC, uh, reduced instruction set computers, as opposed to CISC, complex instruction co- set computers of, uh, Intel fame.
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3:20Hermann HauserGUEST
Uh, John Hennessy, uh, at Stanford and, uh, David Patterson at Berkeley invented RISC, and it's one of the very few occasions where the Americans invented it, but we commercialized it in Europe before the Americans did.
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3:36Hermann HauserGUEST
And so the first, uh, RISC processor, commercial RISC processor, which was developed by Acorn Computers, uh, in Cambridge, hence ARM.
Rodolfo Rosini (CEO, Vaire Computing) is building AI chips on nightmare difficulty
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43:18TomHOST
But they are RISC, they are RISC, yeah
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43:18Rodolfo RosiniGUEST
They used to be CISC, right? And now they're RISC.
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43:20TomHOST
[coughs]
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43:21Rodolfo RosiniGUEST
And, and, and you no longer control the hardware, you control a, an intermediate layer, and then-
358: It's a DE-rail, Not a DB-rail
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62:01Brad ShoemakerHOST
while simultaneously so rapidly closing the performance gap that seemed so large even five years ago.
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62:07Brad ShoemakerHOST
I'll tell you the one example that I can think of or that I have from that video, which is not ARM specific, but it goes to the difference between RISC and CISC processors.
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62:17Brad ShoemakerHOST
Reduced instruction set versus complex instruction set.
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62:21Will SmithHOST
Look, it's the great Usenet and IRC fights of the 90s are coming back to life right now.
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62:26Brad ShoemakerHOST
Yeah, so the quick example I can give is that with RISC, all the instructions are the same length.
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62:32Brad ShoemakerHOST
And so when instructions are being fed into the CPU or being decoded, because this is all stuff I picked up from that video, so I would love for people to help enhance my understanding of this subject, but...
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62:43Brad ShoemakerHOST
As the instructions are being decoded by this processor, when they're all the same size, you can chunk them up and feed them in much more efficiently than with CISC instruction sets like x86, where the instructions are variable length and you can't make assumptions about where instructions begin and end or how long they are or whatever.
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63:02Brad ShoemakerHOST
I gather that the decoding phase on x86 is more complex, and therefore it's probably taking more electricity to run.