Skip to main content
Complex instruction set computer

Complex instruction set computer

Search complete. 7 mentions across 6 episodes found for "Complex instruction set computer".

Oct 20, 2026

Peter MarksGUEST
2:51
This dates back to the early 1980s.
Peter MarksGUEST
2:53
There was actually a British company called Acorn Computers, and they designed it as a simpler and cheaper alternative to the complex instruction sets chips, CISC, which were the ones popular at the time and still popular to some extent now.
Peter MarksGUEST
3:07
In 1990, Apple partnered with them and spun off Arm Holdings to develop a chip for their Newton PDA.
Peter MarksGUEST
3:13
Do you remember the Newton? It was this early PDA with handwriting on it, and that needed performance and low power.
Satya NadellaGUEST
31:48
Uh, it's a great time, by the way, f- to be in computer architecture.
Satya NadellaGUEST
31:52
Um, you know, I think, you know, when I started in, you know, in the industries when the Patterson book first came out, and that was the RISC versus CISC debate.
Satya NadellaGUEST
32:01
I feel like we are back at, uh, sort of a time like this where, uh, you can really rethink, uh, from the physical design of a data center, uh, to, uh, to...
Satya NadellaGUEST
32:13
By the way, the electrons, I mean, one of the p- places where I'm very excited about is the, the efficiency with which we can bring the electrons all the way, uh, to the CPU, uh, so that the tokens are, uh, that much more efficient, right, without all the losses in between.
Artificial IntelligenceNARRATOR
13:14
Architecture feature Apple A18 Pro, MacBook Neo, Apple M4, Base, Intel Core Ultra X9 388H, Panther Lake, born in iPhone 16 Pro, iPad Pro, then MacBook Air Laptops Instruction Set ARMv9, RISC, ARMv9.
Artificial IntelligenceNARRATOR
13:33
2A RISC-X8664 CISC Manufacturing Node TSMC 3nm N3E TSMC 3nm 2nd General Intel 18A TSMC N3E CPU Core 6 2P plus 4E, 10, 4P plus 6E, 16, 4P plus 8E plus 4LPE, NPU AI performance 35 TOPS 38 TOPS approximately 50 TOPS max memory bandwidth 60GB per second 120GB, SUP to approximately 153GB, SA chip designed for a phone sits in the same table as two laptop processors, and it belongs there.
Artificial IntelligenceNARRATOR
14:17
Note the bottom rows, too.
Artificial IntelligenceNARRATOR
14:19
Every one of them carries a neural engine.
Hermann HauserGUEST
2:59
And interestingly, uh, the analogy with ARM, at least on the energy front, is very appropriate.
Hermann HauserGUEST
3:05
Uh, one of the things that happened [laughs], which was actually an American breakthrough, uh, the invention of RISC, uh, reduced instruction set computers, as opposed to CISC, complex instruction co- set computers of, uh, Intel fame.
Hermann HauserGUEST
3:20
Uh, John Hennessy, uh, at Stanford and, uh, David Patterson at Berkeley invented RISC, and it's one of the very few occasions where the Americans invented it, but we commercialized it in Europe before the Americans did.
Hermann HauserGUEST
3:36
And so the first, uh, RISC processor, commercial RISC processor, which was developed by Acorn Computers, uh, in Cambridge, hence ARM.
TomHOST
43:18
But they are RISC, they are RISC, yeah
Rodolfo RosiniGUEST
43:18
They used to be CISC, right? And now they're RISC.
TomHOST
43:20
[coughs]
Rodolfo RosiniGUEST
43:21
And, and, and you no longer control the hardware, you control a, an intermediate layer, and then-
Brad ShoemakerHOST
62:01
while simultaneously so rapidly closing the performance gap that seemed so large even five years ago.
Brad ShoemakerHOST
62:07
I'll tell you the one example that I can think of or that I have from that video, which is not ARM specific, but it goes to the difference between RISC and CISC processors.
Brad ShoemakerHOST
62:17
Reduced instruction set versus complex instruction set.
Will SmithHOST
62:21
Look, it's the great Usenet and IRC fights of the 90s are coming back to life right now.
Brad ShoemakerHOST
62:26
Yeah, so the quick example I can give is that with RISC, all the instructions are the same length.
Brad ShoemakerHOST
62:32
And so when instructions are being fed into the CPU or being decoded, because this is all stuff I picked up from that video, so I would love for people to help enhance my understanding of this subject, but...
Brad ShoemakerHOST
62:43
As the instructions are being decoded by this processor, when they're all the same size, you can chunk them up and feed them in much more efficiently than with CISC instruction sets like x86, where the instructions are variable length and you can't make assumptions about where instructions begin and end or how long they are or whatever.
Brad ShoemakerHOST
63:02
I gather that the decoding phase on x86 is more complex, and therefore it's probably taking more electricity to run.

We value your privacy

We use cookies to understand how you use our platform and to improve your experience. Click “Accept All” to consent, or “Decline non-essential” to opt out of non-essential cookies. Read our Privacy Policy.