Chiplet

7

MENTIONS

4

EPISODES

4

PODCASTS

Sep 8, 2026

Blueshirts Breakaway: A show about the New York Rangers

Blueshirts Breakaway: A show about the New York Rangers

Blueshirts Breakaway EP 563 - Tolvanen, Line Combos & Season Predictions with Ben Norris

Sep 8 · 1 Mention

Greg KaplanHOST

3:06

That, that's all I'm gonna say.

Ryan MeadHOST

3:08

I think it's a really good PR spin for him to play golf with the Chiplets guys who are extremely popular.

Ryan MeadHOST

3:14

No shit.

Greg KaplanHOST

3:14

Sure.

Unknown podcast

Formal Performance and Compile Time Guarantees for Compiler Optimization Heuristics

Aug 23 · 2 Mentions

Ty GaribayHOST

14:50

Think about something like AMD's EPYC processors with multiple chiplets.

Ty GaribayHOST

14:54

There are NUMA effects, there are cross-chiplet bandwidth constraints.

Ty GaribayHOST

14:57

There's a lot going on.

Ty GaribayHOST

14:59

Getting scheduling wrong can mean your task misses in the L3 and has to go all the way to main memory, costing you hundreds of cycles.

Unknown podcast

Cerebras Unveils CS-4 Chip It Claims Is 30 Times Faster Than Nvidia GPUs - Startup Fortune

Aug 21 · 3 Mentions

speaker_1UNKNOWN

7:33

Remember

Skyler MonroeHOST

7:34

how Cerebrus sidesteps this with their wafer scale approach? Well, for most chip companies, the answer has been something different, chiplets and advanced packaging.

Skyler MonroeHOST

7:41

The idea is that instead of one giant chip, you build multiple smaller chips, chiplets that each do a specific job, and then you package them together so tightly that they behave almost like a single chip.

Skyler MonroeHOST

7:51

AMD has been doing this with their processors for years.

Skyler MonroeHOST

7:54

NVIDIA's Blackwell uses a multi-chip module approach, and for AI accelerators specifically, you also need to package in high-bandwidth memory, HBM, which is stacked RAM that sits right next to the compute die to feed it data fast enough to keep up.

Skyler MonroeHOST

9:23

If packaging is the bottleneck, you want to minimize how much packaging complexity your design requires.

Skyler MonroeHOST

9:28

That might favor certain architectures over others.

Skyler MonroeHOST

9:31

It might push more companies toward Cerebras-style monolithic designs, or it might accelerate innovation in new packaging techniques like silicon-photonics interconnects that could reduce the bandwidth constraints between chiplets.

Unknown podcast

How Chip Packaging Became the New Lithography

Aug 16 · 1 Mention

LunaHOST

5:31

Can you talk about that?

LucasHOST

5:34

Yeah, UCIE is the Universal Chiplet Interconnect Express.

LucasHOST

5:38

It's a standard that Intel helped create, along with AMD, TSMC, Samsung, and others.

LucasHOST

5:45

The idea is to make chiplets from different vendors interoperable, so you could mix and match a compute die from one company with memory from another.